The present invention relates to semiconductor devices, and more specifically, to a technique that can be suitably applied to a semiconductor device, for example, with an active element in a wiring layer.
There have been known techniques for providing an active element in a wiring layer of a semiconductor device. Such a semiconductor device can switch its function by use of the active element without changing the layout of semiconductor elements formed at a semiconductor substrate. Thus, the technique can manufacture a plurality of types of semiconductor devices with different functions using the semiconductor substrate with the same layout of the semiconductor elements over the substrate. In this case, the manufacturing costs of the semiconductor devices can be reduced.
For example, Japanese Unexamined Patent Publication No. 2010-141230 discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate, a first wiring layer, a semiconductor layer, a gate insulating film, and a gate electrode. The first wiring layer includes an insulating layer formed over the semiconductor substrate, and a first wiring embedded in the surface of the insulating layer. The semiconductor layer is positioned over the first wiring layer. The gate insulating film is positioned above or below the semiconductor layer. The gate electrode is positioned on the opposite side to the semiconductor layer via the gate insulating film. At this time, the semiconductor layer, the gate insulating film, and the gate electrode form a transistor as the active element. For example, one first wiring can be used as the gate insulating film. Specifically, a cap insulating film for preventing the diffusion of the first wiring layer can be used as the gate insulating film. In that case, the gate insulating film is formed under the semiconductor layer.
In order to reduce power consumption (save power) of the active element in the wiring layer as described above, it is effective to use a CMOS inverter. This is because the use of the CMOS inverter as a switch can suppress the flow-through current through the inverter. The CMOS inverter includes a P-type MOS transistor and an N-type MOS transistor in the same wiring layer. In this case, both a P-type semiconductor layer and an N-type semiconductor layer which are made of different materials are required to be provided in the same wiring layer.
When using the technique disclosed in the above Japanese Unexamined Paten Publication No. 2010-141230, specifically, the following structure can be proposed. The active element, that is, the CMOS inverter in the wiring layer, includes the P-type MOS transistor and the N-type MOS transistor. In each of the MOS transistors, one first wiring in the first wiring layer serves as the gate electrode, the cap insulating film for preventing the diffusion over first wiring layer serves as the gate insulating film, and a semiconductor layer is provided in a predetermined shape over the cap insulating film. The P-type semiconductor layer and the N-type semiconductor layer are disposed spaced apart from each other. Both layers are embedded in an interlayer insulating layer.
In the related art, Non-Patent Document 1 (2012 Symposium on VLSI Technology Digest of Technical Papers, 123-124(2012)) discloses an inverter circuit using an oxide semiconductor layer. Non-Patent Document 2 (2011 Symposium on VLSI Technology Digest of Technical Papers, 120-121(2011)) discloses a LSI incorporating an oxide semiconductor layer in a multilayer wiring layer. Further, Non-Patent Document 3 (2011 IEEE International Electron Devices Meeting (IEDM), 155-158(2011)) discloses a transistor device structure using an oxide semiconductor layer.
PCT Patent Publication WO 2010/010802, Non-Patent Document 4 (Appl. Phys. Lett. 93,032113(2008)), and Non-Patent Document 5 (Appl. Phys. Lett. 97,072111(2010)) discloses a p-channel thin film transistor. The p-channel thin film transistor (field-effect transistor) includes a thin film made of stannous oxide (SnO) deposited as a channel layer over a substrate of the thin film transistor. A source/drain electrode is formed using a laminated film of Ni/Au or a Pt film.